Walter Alexander de Heer from the School of Physics at Georgia Tech has discovered that graphene on the sidewalls of steps on the silicon-terminated face of SiC graphitizes (i.e., forms graphene layers) more readily than on the horizontal surface of silicon-terminated SiC. This growth differential can be exploited to produce narrow and well-annealed graphitic ribbons without complex lithographic steps.
An elongated trench is formed along a predetermined path on the face of the SiC crystal with the dimensions desired to produce a graphitic ribbon. The SiC crystal and trench are annealed to form a ribbon with a V-shaped cross section that forms along the path of the trench. The trench can be formed in a variety of shapes to produce specific ribbons. For example, a bifurcated trench will produce a bifurcated ribbon, and a crossed trench will result in a crossed ribbon. The edges of the ribbons formed with this method have clean edges and demonstrate ballistic charge-transport properties.
- Less damage: Growth of nanoribbons in desired shapes eliminates damage from post-processing to achieve desired dimensions.
- Scalable: 10,000 top-gated graphene transistors on a .24 SiC chip have been demonstrated.
- Room temperature operation: Prototypes exhibit an on-off ratio of 10 and carrier mobilities up to 2,700 cm2/ (V•s) at room temperature.
This technology is useful for next-generation semiconductors and electronic components.
This technology was developed to provide a simpler, faster method to grow ultra-thin graphite layers—also known as multi-layered graphene. An atomic-scale carbon lattice, graphene offers many desirable properties for the fabrication of semiconductors. But, for graphene to be useful in semiconducting applications, its native semi-metallic nature must be modified to introduce a band gap. This band gap can be achieved by creating ultra-thin graphitic ribbons with a width less than 20 nm; however, conventional methods to create ribbons on this scale are ineffective.
Ultra-thin graphene layers grow on silicon carbide (SiC) crystals when they are subjected to a high-temperature annealing process. The layers can be patterned using microelectronics lithography methods; however, this process can damage the edges of narrow graphitic structures and negatively impact the functionality of graphitic ribbons. To overcome these challenges, Georgia Tech researchers sought an improved method for growing graphitic ribbons so this material can be broadly utilized in next-generation electronic applications.