Inventors at Georgia Tech have developed a simple method for bonding aluminum nitride (AlN) to aluminum silicon carbide (AlSiC) directly and added a copper layer to the top of the AlN to create an integrated power electronics substrate and cold plate. This configuration reduces the number of layers required for packaging power electronics modules, while significantly reducing thermal resistance and increasing the mechanical integrity. Reduction in thermal resistance can be achieved by eliminating the DBC and thermal interface layers, so that the dielectric layer, AlN, is directly attached to an AlSiC heat sink/cold plate. This modification capitalizes on similar coefficients of thermal expansion (CTE) for AlN and AlSiC, and the resultant interface between the layers is subjected to low fatigue stress, as most of the copper layers with high CTEs are eliminated. This method has produced a module with fewer layers and is effective for over 1400 thermal cycles (-40°C to 150°C) without any change in bond strength, where other DBC-based modules fail after 100-200 cycles under the same test conditions.
- Customized Substrates: Use of low cost and readily available bonding materials enable easy, customized manufacturing of substrates for packaging power modules.
- Efficient heat transfer: Durable and high thermal conductivity bond material >130 W/mK. Low thermal resistance substrate/cold plate system.
- Longer life cycle: Increases mechanical integrity, reduced CTE mismatch.
- Scalable: Module can be made into any shape or size with integrated heat transfer enhancement features in the AlSiC substrate/cold plate.
- Manufacturing of compact power electronics modules
Power electronic modules are commonly used for the control of electrical power, such as conversion from AC to DC, voltage, current manipulation, etc. Conventional power electronic modules are packaged in configurations that typically contain multiple layers between the electronic device and heat sink, generating significant thermal barrier to heat dissipation. The layers include directly bonded copper (DBC) substrates, a metal heat spreader, thermal interface materials, and a cold plate or heat sink. These layers, contact resistances, and thermal grease increase the thermal resistance from the chip to heat sink and limit the power dissipation and operating temperatures of the device. The use of different material layers in the stack results in a coefficient of thermal expansion (CTE) mismatch between them. This increased thermal resistance and variable operating temperatures combined with the CTE mismatch can lead to both ineffective thermal management and lower mechanical reliability in the form of delamination and cracking between the layers, often in the DBC substrate. Therefore, there is a need for a simpler packaging architecture to reduce the thermal resistance in power electronics modules and improve the mechanical reliability of these modules.