Georgia Tech inventors have created an analog-digital converter with successive approximation, and a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step.
- Better resolution
- Quicker conversion time
- Complementary metal-oxide-semiconductor (CMOS) technologies
- Static RAM
- Digital Logic Circuits
- SAR converters
Traditional digital-to-analog converters (DAC) designs are driven by their applications, and are generally subject to constraints imposed by the trade-off between speed, accuracy, and area. This is especially the case for embedded on chip systems, where die area (a small block of semiconducting material on which a given functional circuit is fabricated) tends to be a major concern. Depending upon the application, speed and/or resolution is often sacrificed for reduced area. However, smaller DAC designs are prone to process variations and random mismatches.