Georgia Tech inventors have developed a capacitor array adapted for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. The tuning of this invention may be performed by changing a reference voltage to which a terminal of the capacitors can be switched. Hence, it is provided that some unit capacitors, within the capacitor ladder network, have a configurable reference voltage which can be changed, so that the number of charge switch changes mimics or equals the effect of different capacitor sizes of the respective capacitors. Consequently, the integral and differential linearity can be improved, which may result in a better efficiency of the SAR ADC. Particularly, and compared to conventional approaches, no additional power consumption or speed penalty is to be expected.
- No additional power consumption
- No speed penalty
- Electronics – SAR converters
Successive approximation register (SAR) converters for analog-digital conversion are frequently used in integrated CMOS devices. The devices provide a reasonable resolution and conversion time and can be implemented by optimally utilizing the advantages of the CMOS technology, (small-sized switches and capacitors having relatively well-defined relative capacitances). Although SAR analog-digital converters (ADCs) can be implemented in different topologies, they generally include at least one capacitor array. The capacitor array may include a unit capacitor array with stages of identical capacitances and one stage with a doubled capacitance, or a capacitance ladder network comprising stages with capacitance values in a mutual relation of a factor of 2n.