Georgia Tech researchers have developed packaging techniques and methods utilizing compliant interconnects with multiple electrical paths in an electronic package. The technology employs compliant interconnects that, unlike solder bumps, can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an under-fill material. The method improves the mechanical reliability of electronic packages in a cost-effective manner, without compromising electrical performance.
- Accommodates the CTE mismatch without requiring under-fill material
- Improves mechanical reliability
- Does not compromise electrical performance
- Electronic packaging
Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller features sizes, as well as innovative on-chip dielectric materials and higher number of interconnects at a reduced pitch without compromising the microelectronics reliability. Thus, it is projected that by the year 2015, the IC feature size will shrink to about 10 nm, and therefore, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 um.